VLSI Reconfigurable FIRP Platform  

An Reconfigurable FIR Filter Design on a Partial Reconfiguration Platform!

This project presents a novel partially reconfigurable FIR filter design that employs dynamic partial reconfiguration.This reconfigurable FIR filter design method using Xilinx Virtex-4 FPGA shows the configuration time improvement, and flexibility by using the dynamic partial reconfiguration method.

Partial reconfiguration design flow.           Block diagram of (a) multiply-accumulate(MAC) modules,
                                                                                 (b) Partial reconfigurable n-order FIR filter.




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