VLSI Reconfigurable FIR Dynamic Partial Config  


A Reconfigurable FIR Filter Design Using  Dynamic Partial Reconfiguration

This project presents a novel partially reconfigurable FIR filter design that employs dynamic partial reconfiguration. Our scope is to implement a low-power, area- efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules. This design method shows the configuration time improvement by small configured slice and good area efficiency as compared to the method of conventional FIR filters.


    FPGA device utilization for several FIR filters.     Module-based partial reconfiguration flow.


 
 
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