VLSI Design Verification  


Design & Verification of 16 Bit RISC Processor

The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.



Instruction set simulator.                               GDB Server Program





   SOLA input Data                                                                                 SOLA output data

 
 
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